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Publications in Math-Net.Ru |
Citations |
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2024 |
1. |
Yu. A. Stepchenkov, Yu. G. Diachenko, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Self-timed counter synthesis formalization”, Sistemy i Sredstva Inform., 34:2 (2024), 66–82 |
2. |
Yu. A. Stepchenkov, D. V. Hilko, Yu. G. Diachenko, N. V. Morozov, D. Yu. Stepchenkov, G. A. Orlov, “Desynchronization methodology at self-timed circuit synthesis”, Sistemy i Sredstva Inform., 34:1 (2024), 33–43 |
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2023 |
3. |
Yu. A. Stepchenkov, D. Yu. Stepchenkov, Yu. G. Diachenko, N. V. Morozov, L. P. Plekhanov, “Replacing synchronous triggers with self-timed counterparts during circuit desynchronization”, Sistemy i Sredstva Inform., 33:4 (2023), 4–15 |
1
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4. |
Yu. A. Stepchenkov, Yu. G. Diachenko, D. Yu. Stepchenkov, D. Yu. Diachenko, G. A. Orlov, “Multiplexed self-timed pipeline”, Sistemy i Sredstva Inform., 33:2 (2023), 4–12 |
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5. |
I. A. Sokolov, Yu. A. Stepchenkov, Yu. G. Diachenko, N. V. Morozov, D. Yu. Diachenko, “Self-timed pipeline with variable stage number”, Sistemy i Sredstva Inform., 33:1 (2023), 4–13 |
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2022 |
6. |
I. A. Sokolov, Y. A. Stepchenkov, Y. V. Rogdestvenski, Y. G. Diachenko, “Approximate evaluation of the efficiency of synchronous and self-timed methodologies in problems of designing failure-tolerant computing and control systems”, Avtomat. i Telemekh., 2022, no. 2, 122–132 ; Autom. Remote Control, 83:2 (2022), 264–272 |
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7. |
I. A. Sokolov, Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, “Synchronous and self-timed pipeline's reliability estimation”, Inform. Primen., 16:4 (2022), 2–7 |
8. |
I. A. Sokolov, Yu. A. Stepchenkov, Yu. G. Diachenko, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Self-timed pipeline's soft error tolerance analysis”, Sistemy i Sredstva Inform., 32:4 (2022), 4–13 |
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9. |
Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Self-timed shift register cases”, Sistemy i Sredstva Inform., 32:3 (2022), 81–91 |
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2021 |
10. |
I. A. Sokolov, Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, A. N. Kamenskih, “The electronic component base of failure resilience digital circuits”, Inform. Primen., 15:4 (2021), 65–71 |
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11. |
D. V. Khilko, Yu. A. Stepchenkov, Yu. I. Shikunov, Yu. G. Diachenko, G. A. Orlov, “Hardware support of fast Fourier transform optimization in a recurrent signal processor”, Sistemy i Sredstva Inform., 31:4 (2021), 71–83 |
12. |
Yu. A. Stepchenkov, N. V. Morozov, Yu. G. Diachenko, D. V. Khilko, “Recurrent signal processor hardware implementation”, Sistemy i Sredstva Inform., 31:3 (2021), 113–122 |
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2020 |
13. |
I. A. Sokolov, Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, “Improvement of self-time circuit soft error tilerance”, Inform. Primen., 14:4 (2020), 63–68 |
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14. |
Yu. A. Stepchenkov, N. V. Morozov, Yu. G. Diachenko, D. V. Khilko, D. Yu. Stepchenkov, “Multicore hybrid recurrent architecture expansion on FPGA”, Sistemy i Sredstva Inform., 30:4 (2020), 95–101 |
15. |
Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Self-timed pipeline immunity to soft errors in its combinational part”, Sistemy i Sredstva Inform., 30:3 (2020), 49–55 |
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16. |
Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Self-timed combinational circuit tolerance to short-term soft errors”, Sistemy i Sredstva Inform., 30:2 (2020), 4–10 |
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2019 |
17. |
Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Indication optimization in multibit self-timed circuits”, Sistemy i Sredstva Inform., 29:4 (2019), 14–27 |
18. |
Yu. A. Stepchenkov, Yu. G. Diachenko, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Sequential self-timed cell characterization”, Sistemy i Sredstva Inform., 29:3 (2019), 104–113 |
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2016 |
19. |
Yu. A. Stepchenkov, A. N. Kamenskih, S. F. Tyurin, Yu. V. Rogdestvenski, “Models of fault-tolerant self-timed circuits”, Sistemy i Sredstva Inform., 26:4 (2016), 19–30 |
20. |
Yu. A. Stepchenkov, A. N. Kamenskih, S. F. Tyurin, Y. G. Diachenko, “Fault-tolerant self-timed serial-parallel port: variants of realization”, Sistemy i Sredstva Inform., 26:3 (2016), 48–59 |
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2015 |
21. |
D. V. Khilko, Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. I. Shikunov, N. V. Morozov, “Hardware and software modeling and testing of the recurrent operational device”, Sistemy i Sredstva Inform., 25:4 (2015), 78–90 |
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2014 |
22. |
I. Sokolov, Y. Stepchenkov, S. Bobkov, V. Zakharov, Y. Diachenko, Y. Rogdestvenski, A. Surkov, “Implementation basis of exaflops class supercomputer”, Inform. Primen., 8:1 (2014), 45–70 |
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23. |
Y Stepchenkov, Y Diachenko, Y. Rogdestvenski, N. Morozov, D. Stepchenkov, A. Rogdestvenskene, A. Surkov, “Self-timed fused multiply-add unit: Practical implementation”, Sistemy i Sredstva Inform., 24:3 (2014), 63–77 |
4
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24. |
I. Sokolov, Y. Stepchenkov, S. Bobkov, Y. Rogdestvenski, Y. Diachenko, “Fused multiply-add: Methodological aspects”, Sistemy i Sredstva Inform., 24:3 (2014), 44–62 |
25. |
V. S. Petrukhin, D. Y. Stepchenkov, N. V. Morozov, Y. A. Stepchenkov, “System verification tools for recurrent signal processor”, Sistemy i Sredstva Inform., 24:2 (2014), 55–66 |
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2013 |
26. |
D. Khilko, Yu. Stepchenkov, “Theoretical aspects of programming methodology development for recurrent architecture”, Sistemy i Sredstva Inform., 23:2 (2013), 133–153 |
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2012 |
27. |
D. Khilko, Yu. Stepchenkov, “Dataflow architecture model and its usage with a word recognizer program as an example”, Sistemy i Sredstva Inform., 22:2 (2012), 48–57 |
1
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28. |
R. A. Zelenov, A. A. Prokofyev, Yu. A. Stepchenkov, V. N. Volchek, “Exceptions fixation in recurrent dataflow processor”, Sistemy i Sredstva Inform., 22:1 (2012), 49–61 |
29. |
Yu. G. Dyachenko, N. V. Morozov, D. Yu. Stepchenkov, Yu. A. Stepchenkov, “Tools for self-timed cells characterization”, Sistemy i Sredstva Inform., 22:1 (2012), 38–48 |
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2011 |
30. |
Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, N. V. Morozov, “Self-timed analysis of some types of digital device”, Sistemy i Sredstva Inform., 21:1 (2011), 74–83 |
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2010 |
31. |
Yu. Stepchenkov, V. Volchek, V. Petrukhin, A. Prokofyev, R. Zelenov, “Hardware maintenance for digital processing of speech signals in the recurrent dataflow processor”, Sistemy i Sredstva Inform., 20:1 (2010), 31–47 |
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32. |
R. Zelenov, Yu. Stepchenkov, V. Volchek, D. Hilko, A. Shneyder, A. Prokofyev, “System of capsule programming and debugging”, Sistemy i Sredstva Inform., 20:1 (2010), 24–30 |
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33. |
Yu. Stepchenkov, Yu. Dyachenko, Yu. Rozhdestvenski, N. Morozov, D. Stepchenkov, “Designing of the delay-independent computing device”, Sistemy i Sredstva Inform., 20:1 (2010), 5–23 |
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2008 |
34. |
Yu. A. Stepchenkov, V. S. Petrukhin, D. V. Hilko, “Selection of programming languages for representing parallel algorithms for recurrent signal processor”, Sistemy i Sredstva Inform., 2008, no. supplementary issue, 149–158 |
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35. |
V. S. Petrukhin, Yu. A. Stepchenkov, V. N. Volchek, A. A. Prokofyev, R. A. Zelenov, “Peculiarities of realization of the main modules of recurrent signal processor on the programmed logic integrated circuit (PLD)”, Sistemy i Sredstva Inform., 2008, no. supplementary issue, 130–148 |
1
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36. |
Yu. A. Stepchenkov, V. S. Petrukhin, “The features of hybrid version of recurrent signal processor realized on the programmed logic integrated circuit (PLD)”, Sistemy i Sredstva Inform., 2008, no. supplementary issue, 118–129 |
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37. |
Yu. A. Stepchenkov, Yu. G. Dyachenko, Yu. V. Rozhdestvensky, N. V. Morozov, D. Yu. Stepchenkov, “Quasi self-timed realization of the device for division and square-root generation”, Sistemy i Sredstva Inform., 2008, no. 18, 234–260 |
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2007 |
38. |
Yu. A. Stepchenkov, Yu. G. Dyachenko, V. S. Petrukhin, “Self-timed sequential circuits: Development experience and design guideline”, Sistemy i Sredstva Inform., 2007, no. 17, 503–529 |
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2006 |
39. |
V. S. Petrukhin, Yu. A. Stepchenkov, N. V. Morozov, D. Yu. Stepchenkov, “System for self-timed integrated circuits testing”, Sistemy i Sredstva Inform., 2006, no. 16, 486–495 |
40. |
L. P. Plekhanov, Yu. A. Stepchenkov, “Experimental testing of some strictly self-timed circuits features”, Sistemy i Sredstva Inform., 2006, no. 16, 476–485 |
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41. |
Yu. V. Rozhdestvensky, N. V. Morozov, Yu. A. Stepchenkov, A. V. Rozhdestvenskene, “Universal subsystem for self-timed circuits analysis”, Sistemy i Sredstva Inform., 2006, no. 16, 463–475 |
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2008 |
42. |
A. V. Filin, Yu. A. Stepchenkov, V. S. Petrukhin, “The history and results of the development of home made 32-bit personal computer”, Sistemy i Sredstva Inform., 2008, no. 18, 281–310 |
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