Multiplexed self-timed pipeline

The article considers the problem of correct practical implementation of a self-timed pipeline with multiplexing of actively operating stages taking into account the circuitry limitations imposed by the technology used. Complementing two parallel branches with a self-timed marker FIFO (First-Input–First-Output) reduces the average latency of the pipeline and ensures its operation is self-timed. With sufficient FIFO capacity, successive data portions can be processed simultaneously by different pipeline's branches. The circuitry solutions of the multiplexed pipeline's individual units guarantee pipeline practical feasibility in any complementary metal – oxide – semiconductor process at domestic semiconductor factories.