Self-timed pipeline with variable stage number

The article considers the self-timed circuit's performance improvement problem. As in synchronous circuits, an effective way to improve performance is to use a pipeline to implement multistage input data processing. The article analyzes possible options for dynamical reduction of the number of actively operating stages under certain conditions determined by the processed data value or an external signal. The estimates show that the efficiency of using an optionally variable number of pipeline stages depends on the number of bypassed stages and the probability of an event allowing this bypassing. In particular, replacing two successive pipeline stages with one parallel stage becomes expedient if it occurs in at least 63% of data processing operations and bypassing two or more stages reduces the average pipeline's latency if it occurs in at least 43% of operations.