Self-timed analysis of some types of digital device

An approach to verification of digital circuits for self-timed by means of software tools that implement the event-based method is presented. It is shown that relatively simple means provide a total-lot test fullness of the self-timed analysis for shift registers as well as for memory registers. A technique for debugging an arbitrary circuit during its self-timed analysis is suggested. The necessity of a hierarchical approach to self-timed analysis of a complicated circuit is grounded.