Replacing synchronous triggers with self-timed counterparts during circuit desynchronization

Self-timed (ST) digital circuits have a number of advantages in comparison with synchronous counterparts and become a promising basis for the reliable computing systems implementation operating in extreme conditions. The lack of effective tools for automated synthesis of ST circuits convenient for use by developers trained in computer-aided design of the synchronous circuits significantly hinders the introduction of ST circuits into digital circuit development practice. The approach to the ST circuit synthesis based on the transformation of the original synchronous Verilog description of the circuit operation algorithm into the ST implementation according to formalized rules in automatic mode with minimal interactive participation of the developer provides a quick ST solution with acceptable characteristics and does not require deep knowledge of self-timing from the designer. It relies on the basic principles of ST circuits design and heuristic methods for their development. One of the important and controversial stages of ST circuit design in this approach is the replacement of synchronous latches and flip-flops by their ST counterparts. For this purpose, the authors propose to use the method of tabular formalized correspondence based on a ready-made library of ST latches and flip-flops and analysis of their environment.