Self-timed combinational circuit tolerance to short-term soft errors

The paper considers self-timed (ST) complementary metal–oxide–semiconductor (CMOS) combinational circuit tolerance to short-term soft errors caused by the external sources or internal noises that do not lead to semiconductor structure destruction. The paper discusses the consequences of physical causes impact, leading to soft errors in a chip manufactured by the 65-nanometer and below CMOS process. It introduces soft error classification in CMOS ST combinational circuits depending on their appearance time and the type of failure. Self-timed circuits have a higher degree of resistance to short-term soft errors than their synchronous counterparts due to the two-phase operation discipline, request-acknowledge interaction, and dual-rail information signal coding. The paper proposes circuitry and layout methods ensuring the lowering of CMOS ST combinational circuit sensitivity to soft errors due to the guaranteed absence of the bipolar influence of the soft error source on the cells forming dual-rail signals and on their wires in the circuit layout.