Improvement of self-time circuit soft error tilerance

The paper considers a tolerance of self-timed (ST) circuits fabricated with complementary metal–oxide–semiconductor (CMOS) process to short-term soft errors generated by external causes, namely, nuclear particles, cosmic rays, electromagnetic pulses, and noises. Pipeline implementation is usual for practical ST-circuits. Its control bases on handshake between pipeline stages and two-phase operation discipline with a sequence of the working phase and spacer one. Combinational part of the pipeline stage uses dual-rail information signal coding with a spacer. The pipeline stage indication part acknowledges a switching completion of all stage cells, fired at the current operation phase, and generates handshake signals in ST-pipeline stages control. The paper discusses the physical causes of the short-term soft errors. It analyzes soft error types that may appear in CMOS ST-circuits fabricated with 65-nanometer and below standard bulk process. The tolerance level of the proposed soft error hardened ST-register bits is discussed and compared. The paper suggests circuitry and layout techniques improving ST-pipeline soft error tolerance and estimates soft error immunity level for all pipeline parts depending on soft error location.