The features of hybrid version of recurrent signal processor realized on the programmed logic integrated circuit (PLD)

The state of the art architectures intended for parallel calculations are analyzed. The structure of a compromise (hybrid) variant of implementation of the recurrent signal processor's architecture developed by the Institute of Informatics Problems of the Russian Academy of Sciences is offered. This article is considered as an introductory one. Concrete results of implementation of separate parts of suggested structure are presented in two other articles in this book.