Desynchronization methodology at self-timed circuit synthesis

Self-timed (ST) digital circuits have undoubted advantages over synchronous counterparts. However, ST circuit synthesis currently requires the user to have deep knowledge in the ST circuit technology field, since its automation level is still far from the level achieved in industrial computer-aided design systems for synchronous circuits and is focused on assigning the synthesized circuit behavior in specific formats. Designing of ST circuits is more labor-intensive and specific in comparison with synchronous circuits because of the need to adhere to the strict principles for their implementation. Desynchronization is an important stage in the ST circuit synthesis based on the original Verilog description of the circuit operation algorithm. It provides circuit separation from the global clock and asynchronous request-acknowledge interaction usage preparation. The article considers the desynchronization implementation methodology and its formalization principles. The proposed method ensures an ST circuit correct construction based on heuristic algorithms determining the relationships between functional blocks in the synthesized circuit and organizing their interaction in strict accordance with the ST circuit operation discipline.