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Publications in Math-Net.Ru |
Citations |
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2022 |
| 1. |
I. A. Sokolov, Y. A. Stepchenkov, Y. V. Rogdestvenski, Y. G. Diachenko, “Approximate evaluation of the efficiency of synchronous and self-timed methodologies in problems of designing failure-tolerant computing and control systems”, Avtomat. i Telemekh., 2022, no. 2, 122–132  ; Autom. Remote Control, 83:2 (2022), 264–272 |
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| 2. |
I. A. Sokolov, Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, “Synchronous and self-timed pipeline's reliability estimation”, Inform. Primen., 16:4 (2022), 2–7 |
| 3. |
Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Self-timed shift register cases”, Sistemy i Sredstva Inform., 32:3 (2022), 81–91 |
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2021 |
| 4. |
I. A. Sokolov, Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, A. N. Kamenskih, “The electronic component base of failure resilience digital circuits”, Inform. Primen., 15:4 (2021), 65–71 |
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2020 |
| 5. |
I. A. Sokolov, Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, “Improvement of self-time circuit soft error tilerance”, Inform. Primen., 14:4 (2020), 63–68 |
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| 6. |
Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Self-timed pipeline immunity to soft errors in its combinational part”, Sistemy i Sredstva Inform., 30:3 (2020), 49–55 |
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| 7. |
Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Self-timed combinational circuit tolerance to short-term soft errors”, Sistemy i Sredstva Inform., 30:2 (2020), 4–10 |
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2019 |
| 8. |
Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Indication optimization in multibit self-timed circuits”, Sistemy i Sredstva Inform., 29:4 (2019), 14–27 |
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2016 |
| 9. |
Yu. A. Stepchenkov, A. N. Kamenskih, S. F. Tyurin, Yu. V. Rogdestvenski, “Models of fault-tolerant self-timed circuits”, Sistemy i Sredstva Inform., 26:4 (2016), 19–30  |
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2014 |
| 10. |
I. Sokolov, Y. Stepchenkov, S. Bobkov, V. Zakharov, Y. Diachenko, Y. Rogdestvenski, A. Surkov, “Implementation basis of exaflops class supercomputer”, Inform. Primen., 8:1 (2014), 45–70 |
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| 11. |
Y Stepchenkov, Y Diachenko, Y. Rogdestvenski, N. Morozov, D. Stepchenkov, A. Rogdestvenskene, A. Surkov, “Self-timed fused multiply-add unit: Practical implementation”, Sistemy i Sredstva Inform., 24:3 (2014), 63–77 |
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| 12. |
I. Sokolov, Y. Stepchenkov, S. Bobkov, Y. Rogdestvenski, Y. Diachenko, “Fused multiply-add: Methodological aspects”, Sistemy i Sredstva Inform., 24:3 (2014), 44–62 |
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2011 |
| 13. |
Yu. V. Rogdestvensky, N. V. Morozov, A. V. Rogdestvenskene, “Particularities of taxonomic self-timed circuits analysis”, Sistemy i Sredstva Inform., 21:1 (2011), 92–104 |
| 14. |
Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, N. V. Morozov, “Self-timed analysis of some types of digital device”, Sistemy i Sredstva Inform., 21:1 (2011), 74–83 |
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2010 |
| 15. |
Yu. Stepchenkov, Yu. Dyachenko, Yu. Rozhdestvenski, N. Morozov, D. Stepchenkov, “Designing of the delay-independent computing device”, Sistemy i Sredstva Inform., 20:1 (2010), 5–23 |
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2008 |
| 16. |
Yu. A. Stepchenkov, Yu. G. Dyachenko, Yu. V. Rozhdestvensky, N. V. Morozov, D. Yu. Stepchenkov, “Quasi self-timed realization of the device for division and square-root generation”, Sistemy i Sredstva Inform., 2008, no. 18, 234–260 |
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2006 |
| 17. |
Yu. V. Rozhdestvensky, N. V. Morozov, Yu. A. Stepchenkov, A. V. Rozhdestvenskene, “Universal subsystem for self-timed circuits analysis”, Sistemy i Sredstva Inform., 2006, no. 16, 463–475 |
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