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Publications in Math-Net.Ru |
Citations |
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2024 |
| 1. |
Yu. A. Stepchenkov, Yu. G. Diachenko, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Self-timed up counter implementation”, Sistemy i Sredstva Inform., 34:3 (2024), 123–135  |
| 2. |
Yu. A. Stepchenkov, Yu. G. Diachenko, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Self-timed counter synthesis formalization”, Sistemy i Sredstva Inform., 34:2 (2024), 66–82 |
| 3. |
Yu. A. Stepchenkov, D. V. Hilko, Yu. G. Diachenko, N. V. Morozov, D. Yu. Stepchenkov, G. A. Orlov, “Desynchronization methodology at self-timed circuit synthesis”, Sistemy i Sredstva Inform., 34:1 (2024), 33–43 |
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2023 |
| 4. |
Yu. A. Stepchenkov, D. Yu. Stepchenkov, Yu. G. Diachenko, N. V. Morozov, L. P. Plekhanov, “Replacing synchronous triggers with self-timed counterparts during circuit desynchronization”, Sistemy i Sredstva Inform., 33:4 (2023), 4–15 |
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| 5. |
Yu. A. Stepchenkov, Yu. G. Diachenko, D. Yu. Stepchenkov, D. Yu. Diachenko, G. A. Orlov, “Multiplexed self-timed pipeline”, Sistemy i Sredstva Inform., 33:2 (2023), 4–12 |
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2022 |
| 6. |
I. A. Sokolov, Yu. A. Stepchenkov, Yu. G. Diachenko, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Self-timed pipeline's soft error tolerance analysis”, Sistemy i Sredstva Inform., 32:4 (2022), 4–13 |
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| 7. |
Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Self-timed shift register cases”, Sistemy i Sredstva Inform., 32:3 (2022), 81–91 |
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2020 |
| 8. |
Yu. A. Stepchenkov, N. V. Morozov, Yu. G. Diachenko, D. V. Khilko, D. Yu. Stepchenkov, “Multicore hybrid recurrent architecture expansion on FPGA”, Sistemy i Sredstva Inform., 30:4 (2020), 95–101 |
| 9. |
Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Self-timed pipeline immunity to soft errors in its combinational part”, Sistemy i Sredstva Inform., 30:3 (2020), 49–55 |
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| 10. |
Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Self-timed combinational circuit tolerance to short-term soft errors”, Sistemy i Sredstva Inform., 30:2 (2020), 4–10 |
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2019 |
| 11. |
Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Indication optimization in multibit self-timed circuits”, Sistemy i Sredstva Inform., 29:4 (2019), 14–27 |
| 12. |
Yu. A. Stepchenkov, Yu. G. Diachenko, N. V. Morozov, D. Yu. Stepchenkov, D. Yu. Diachenko, “Sequential self-timed cell characterization”, Sistemy i Sredstva Inform., 29:3 (2019), 104–113 |
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2014 |
| 13. |
Y Stepchenkov, Y Diachenko, Y. Rogdestvenski, N. Morozov, D. Stepchenkov, A. Rogdestvenskene, A. Surkov, “Self-timed fused multiply-add unit: Practical implementation”, Sistemy i Sredstva Inform., 24:3 (2014), 63–77  |
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| 14. |
V. S. Petrukhin, D. Y. Stepchenkov, N. V. Morozov, Y. A. Stepchenkov, “System verification tools for recurrent signal processor”, Sistemy i Sredstva Inform., 24:2 (2014), 55–66 |
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2012 |
| 15. |
Yu. G. Dyachenko, N. V. Morozov, D. Yu. Stepchenkov, Yu. A. Stepchenkov, “Tools for self-timed cells characterization”, Sistemy i Sredstva Inform., 22:1 (2012), 38–48 |
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2010 |
| 16. |
Yu. Stepchenkov, Yu. Dyachenko, Yu. Rozhdestvenski, N. Morozov, D. Stepchenkov, “Designing of the delay-independent computing device”, Sistemy i Sredstva Inform., 20:1 (2010), 5–23 |
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2008 |
| 17. |
Yu. A. Stepchenkov, Yu. G. Dyachenko, Yu. V. Rozhdestvensky, N. V. Morozov, D. Yu. Stepchenkov, “Quasi self-timed realization of the device for division and square-root generation”, Sistemy i Sredstva Inform., 2008, no. 18, 234–260 |
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2006 |
| 18. |
V. S. Petrukhin, Yu. A. Stepchenkov, N. V. Morozov, D. Yu. Stepchenkov, “System for self-timed integrated circuits testing”, Sistemy i Sredstva Inform., 2006, no. 16, 486–495 |
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