Modeling of VLSI at different design levels.
Verification of projects and development of tests of VLSI control at RTL-, functional-logical and switching levels.
Biography
Candidate of Technical Sciences (1984),
Senior Researcher (1989),
Associate Professor (1993)
Scientific direction:
•Logical design.
•Simulation.
•Test diagnosis of the objects of digital electronics at different levels of design.
•Verification of projects.
•Research and development of methods, algorithms and software for VLSI simulation.
Main publications:
L.A. Zolotorevich, “Project verification and construction of superchip tests at the RTL level”, Automation and Remote Control, 74:1 (2013), 113-122
Zolotorevich L.A., Il'inkova A. V., “Development of tests for VLSI circuit testability at the upper design levels Automation and Remote Control.”, Automation and Remote Control, 71:9 (2010), 1888-1898
Zolotorevich, L.A., Yukhnevich D.I., “Switch-level VLSI quasistatic simulation methods: Comparative accuracy of models”, Automation and Remote Control, 9:9 (1998)
L. A. Zolotorevich, “Project verification and construction of superchip tests at the RTL level”, Avtomat. i Telemekh., 2013, no. 1, 146–158; Autom. Remote Control, 74:1 (2013), 113–122
L. A. Zolotorevich, A. V. Il'inkova, “Development of tests for VLSI circuit testability at the upper design levels”, Avtomat. i Telemekh., 2010, no. 9, 162–173; Autom. Remote Control, 71:9 (2010), 1888–1898
L. A. Zolotorevich, D. I. Yukhnevich, “Switch-level VLSI quasistatic simulation methods: comparative accuracy of models”, Avtomat. i Telemekh., 1998, no. 9, 130–141; Autom. Remote Control, 59:9 (1998), 1308–1316
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