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Avtomatika i Telemekhanika, 2013, Issue 1, Pages 146–158
(Mi at4291)
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This article is cited in 2 scientific papers (total in 2 papers)
Safety, Viability, Reliability, Technical Diagnostics
Project verification and construction of superchip tests at the RTL level
L. A. Zolotorevich Belarus State University, Minsk, Belarus
Abstract:
Methods were proposed for project verification and directed design of the superchip tests represented in VHDL at the RTL level. The problem of test design and project verification was solved on the basis of the CNF-satisfiability of some system of Boolean functions.
Citation:
L. A. Zolotorevich, “Project verification and construction of superchip tests at the RTL level”, Avtomat. i Telemekh., 2013, no. 1, 146–158; Autom. Remote Control, 74:1 (2013), 113–122
Linking options:
https://www.mathnet.ru/eng/at4291 https://www.mathnet.ru/eng/at/y2013/i1/p146
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Statistics & downloads: |
Abstract page: | 306 | Full-text PDF : | 101 | References: | 48 | First page: | 20 |
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