Vestnik Yuzhno-Ural'skogo Gosudarstvennogo Universiteta. Seriya "Vychislitelnaya Matematika i Informatika"
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Vestnik Yuzhno-Ural'skogo Gosudarstvennogo Universiteta. Seriya "Vychislitelnaya Matematika i Informatika", 2014, Volume 3, Issue 2, Pages 117–121 (Mi vyurv43)  
This article is cited in 1 scientific paper (total in 1 paper)

Brief Reports

Automatic mapping programs onto a processor with an FPGA accelerator

D. V. Dubrov, A. S. Roshal, B. Ya. Steinberg, R. B. Steinberg

Southern Federal University (Rostov-on-Don, Russian Federation)
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Abstract: A problem of automatic high level program mapping onto a CPU with an FPGA accelerator is considered in this work. For such a mapping an HDL code generator from a parallelizing system's internal representation is being developed and used.
Keywords: social network analysis, information retrieval, data mining, expert finding, popularity analysispeline computing, high-level synthesis, parallelizing compiler, FPGA, VHDL.
Received: 07.03.2014
Document Type: Article
UDC: 681.3
Language: Russian
Citation: D. V. Dubrov, A. S. Roshal, B. Ya. Steinberg, R. B. Steinberg, “Automatic mapping programs onto a processor with an FPGA accelerator”, Vestn. YuUrGU. Ser. Vych. Matem. Inform., 3:2 (2014), 117–121
Citation in format AMSBIB
\Bibitem{DubRosSte14}
\by D.~V.~Dubrov, A.~S.~Roshal, B.~Ya.~Steinberg, R.~B.~Steinberg
\paper Automatic mapping programs onto a processor with an FPGA accelerator
\jour Vestn. YuUrGU. Ser. Vych. Matem. Inform.
\yr 2014
\vol 3
\issue 2
\pages 117--121
\mathnet{http://mi.mathnet.ru/vyurv43}
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  • https://www.mathnet.ru/eng/vyurv/v3/i2/p117
    • This publication is cited in the following 1 articles:
    Citing articles in Google Scholar: Russian citations, English citations
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    		Vestnik Yuzhno-Ural'skogo Gosudarstvennogo Universiteta. Seriya "Vychislitelnaya Matematika i Informatika"
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