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Vestnik Yuzhno-Ural'skogo Universiteta. Seriya Matematicheskoe Modelirovanie i Programmirovanie, 2010, Issue 6, Pages 41–53
(Mi vyuru227)
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This article is cited in 1 scientific paper (total in 1 paper)
Russian 3D-torus interconnect with globally addressable memory support
A. A. Korzha, D. V. Makagona, A. A. Borodin, I. A. Zhabin, E. R. Kushtanov, E. L. Syromyatnikov, E. V. Cheryomushkina a Scientific and Research Centre of Electronic Computer Technology, Moscow
Abstract:
This paper gives the overview and early results of prototyping of the 3D-torus interconnect developed in NICEVT, Moscow. This interconnect was designed to be equally effective in small-size computing clusters and petascale systems. The key features of the interconnect are high fault-tolerance, high message rate per core supported by host adapter and hardware support for globally addressable memory provided via SHMEM parallel programming library.
Keywords:
interconnection network, supercomputer, 3D-torus, globally addressable memory.
Received: 07.04.2010
Citation:
A. A. Korzh, D. V. Makagon, A. A. Borodin, I. A. Zhabin, E. R. Kushtanov, E. L. Syromyatnikov, E. V. Cheryomushkina, “Russian 3D-torus interconnect with globally addressable memory support”, Vestnik YuUrGU. Ser. Mat. Model. Progr., 2010, no. 6, 41–53
Linking options:
https://www.mathnet.ru/eng/vyuru227 https://www.mathnet.ru/eng/vyuru/y2010/i6/p41
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Abstract page: | 122 | Full-text PDF : | 55 | References: | 24 |
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