The compressive sensing approach for the FPGA-based image hardware encoder

The image compression standard approaches are considered. The complexity estimation for the FPGA implementation are presented. The new approach is based on Compressive Sensing (CS) principles to reduce the image data dimension are suggested. The CS encoder model using the pseudorandom measurement algorithm is implemented. The convex algorithm with the minimum reconstruction error criterion to reconstruct the original signal from its sparse representation is matched. The FPGA-based hardware CS encoder is developed. The utilized logic for the 2-D–DCT and CS coders are compared. The experimental data is presented. The general advantages and shortcomings of the hardware design implementation for CS encoder is discussed.