Algorithms and schemes of adding numbers in an arithmetic logic unit with the use of the system of residual classes

The algorithm of adding two numbers in the system of residual classes taking into account the possibility of parallel computing is presented; the block diagram of a hardware implementation of the algorithm is shown. The upper bound on the number of cycles of the algorithm depending on the number of processors used and bit numbers is fixed. This estimation can be used to identify a desired number of parallel processors (cores) depending on the time constraints on the operation of addition and its related arithmetic operations.