Project code protection for ultrasonic medical devices, designed at PLIC of FPGA type, with the help of PRS generator

Programmable logic integrated chips (PLIC) are widely used in designing and manufacturing of ultrasonic medical scanners. It is a combination of logic elements and memory located at the same chip. In this paper the author offers a project protection mechanism realized at FPGA PLIC, based on the interaction of the mentioned PLIC with PLIC of CPLD type, and providing the device nonoperability when the interaction does not meet a certain criterion. The application of pseudorandom sequence generator (PRSG) is a good solution of the problem. To realization the protection mechanism it is offered to use two identical PRS generators (PRSG) simultaneously set in start state (by command from FPGA PLIC) and clocked from the same clock generator. The outlets of these PRSGs are combined per scheme excluding OR and locked at trigger clocked by frequency front of which is shifted relative to the frequency front clocking PRSG. Such solution will allow to avoid problems concerning time of propagation in scheme and to get stable level at trigger outlet when sequences of PRSG at FPGA and CPLD PLIC are identical.