Self-timed shift register cases

The paper discusses the problems of designing and using self-timed (ST) shift registers. Self-timed circuits have their specifics: two-phase work discipline, redundant information coding, etc. Due to this, they have some advantages compared with synchronous counterparts: independence of behavior from cell delays, detection of any stuck faults, etc. The article considers implementation options for the ST shift register with various options, including setting to a spacer and presetting a fixed value in each bit of the shift register. The proposed options have different functionality, complexity, and performance. Shift registers based on RS-flip-flops have minimal hardware costs, while shift registers based on hysteretic triggers have better performance. The article analyzes shift register's characteristics and substantiates recommendations for their use as a serial-to-parallel port, parallel-to-serial port, or FIFO (First Input, First Output).