Recurrent signal processor hardware implementation

The paper presents the results of hybrid architecture of recurrent multicore signal processor (HARMSP) hardware implementation as register transfer level VHDL-model and its prototype approbation on a development board with Intel Arria10 field-programmable gate array (FPGA). HARMSP consists of von-Neumann master processor at control architecture level and data-flow recurrent processor with four computing sections at operational level. Hardware HARMSP model is a complex of software or hardware control processor (CP) implementation and operational level VHDL-model. CAD Quartus (Intel) provides the software CP implementation on FPGA, whereas SoC FPGA on the development board contains the hardware CP implementation as dual-core Cortex-A9 processor.