Multicore hybrid recurrent architecture expansion on FPGA

The paper presents the result of modification of the multicore hybrid architecture for recurrent signal processing (HARSP) and discusses its approbation as a prototype on the next-generation HAN Pilot Platform development board with FPGA (field-programmable gate array) Intel Arria10 SoC 10AS066K3F40E2SG on the basis of the register transfer level VHDL (very high speed integrated circuits) model. Hybrid architecture for recurrent signal processing contains the control level, implemented as von Neumann processor, and the operational level represented by the data-flow processor with eight computing cores. A capsule distributor combines all computing cores. It provides algorithmic capsule explication into a parallel-serial command flow and processes 32-bit data. Hardware implementation of the control level dual-core processor Cortex-A9 improved HARSP performance radically and increased data processing accuracy due to using 32-bit fixed-point operands. Modified HARSP VHDL-model approbation on a typical data processing application, namely, isolated word recognition, proved HARSP high efficiency in real-time mode operation.