Indication optimization in multibit self-timed circuits

Indication subcircuit in self-timed (ST) circuits provides both control of the completion of switching all their cells to the current phase and control of their functional blocks interaction. An increase of the ST-circuit capacity leads to rising contribution of the indication subcircuit to the circuit's transient delay. The paper discusses the optimization of the indication subcircuit and *the organization of the ST-pipeline intended for improving performance of the whole circuit. Register bit for storing intermediate data in the pipeline stages is implemented on the basis of hysteretic trigger instead of traditional RS-trigger. Such register bit has less complexity and provides storing both the work and the spacer states of a dual-rail data. Discipline of the pipeline stage phase control by means of total indication outputs of the adjacent pipeline stages is replaced with bit-wise indication and bit-wise control principle, which utilizes the parallelism of the calculations in the multibit ST-circuits. Proposed solutions essentially improve ST-circuits performance due to a slight complication of the indication subcircuit.