Models of fault-tolerant self-timed circuits

The development of both the reliable and the energy-efficient computing systems is one of most important tasks in the XXI century. The usage of self-timed circuits makes it possible to improve energy-efficiency of a computing system. However, the complexity increase in not fault-tolerant self-timed circuits leads to decrease of reliability. The fault-tolerant self-timed implementation of digital devices makes it possible to increase not only reliability but also the complex index “energy–consumption/reliability.” The further development of synthesis methods of fault-tolerant self-timed circuits will allow to compensate the negative effects of self-timed circuit's development by the positive effect of complex index increasing. The paper describes the models and algorithms of fault detection which are developed to improve validity and reliability of actively fault-tolerant self-timed circuits.