Fault-tolerant non-blocking three-dimensional sparse hypercube

A system network is proposed in the form of a non-blocking fault-tolerant three-dimensional generalized $p$-ary hypercube with a single processor in each node of the hypercube. In any non-blocking network, data between processors is transmitted over direct channels with the lowest latencies and without intermediate buffering. Networks with the topology of a generalized hypercube have the smallest lengths of direct channels and the smallest transmission delays. The structure of this hypercube based on networks with the topology of a quasi-complete graph is developed, which allows exchanging the number of processors for the number of different direct channels between any processors and setting the channel and node fault tolerance of the network. The parameters of quasi-complete graphs that exist for any $p$-identity of a hypercube are given. As a result, a network structure is proposed in the form of a sparse $p$-ary hypercube with a number of nodes slightly smaller than in a regular $p$-ary hypercube. The sparse hypercube is designed as a fault-tolerant system network for a single-chip processor accelerator with several hundred cores. A procedure and an algorithm for the laying of conflict-free direct channels through dynamic local packet self-routing has been developed, in which the nodes do not interact with each other and use only extended routing information from the packets.