Classification of loops with one statement for executing on the processor with programmable accelerator

The classification of program cycles for an optimizing compiler for a processor with a programmable accelerator is considered. Such a processor can be a system on a crystal that contains both computational cores and a programmable circuit. The programmable accelerator is tuned to the architecture of the reconfigurable pipeline.
The classification according to regular information dependencies is specified. For each class of cycles, the possibility of pipelining is considered. If immediate pipelining is impossible, then the question discussed about transformations of such a cycle to a pipeline-type view using OPC (Optimizing the parallelizing system). Information dependencies in the loop affect the architecture of the pipeline that implements the loop.
The compiler differs from conventional by the presence of converter from a high level programming language to hardware description language. It should also have a library jf drivers for data transfer from the CPU to FPGA and back. Numerical experiment for one of the loop classes demonstrated a double acceleration. (In Russian).