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Prikladnaya Diskretnaya Matematika. Supplement, 2013, Issue 6, Pages 36–38 (Mi pdma98)  
Mathematical Methods of Cryptography

FPGA implementation of FAPKC symmetric equivalent

D. S. Kovalevab

a Tomsk State University
b JSC "Information Satelline Systems Reshetnev Company", Zheleznogorsk
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Abstract: FPGA implementation of the FAPKC symmetric equivalent (called FASKC) is presented. The throughput/area comparison of the FASKC with the other finite automata cryptosystems is made. The FPGA implementation comparison of the FASKC, AES and other contemporary block ciphers is given.
Keywords: non-linear automaton, invertible with delay automaton, finite automata cryptosystem, FAPKC, FASKC, PLD, FPGA, VHDL.
Document Type: Article
UDC: 004.056.55
Language: Russian
Citation: D. S. Kovalev, “FPGA implementation of FAPKC symmetric equivalent”, Prikl. Diskr. Mat. Suppl., 2013, no. 6, 36–38
Citation in format AMSBIB
\Bibitem{Kov13}
\by D.~S.~Kovalev
\paper FPGA implementation of FAPKC symmetric equivalent
\jour Prikl. Diskr. Mat. Suppl.
\yr 2013
\issue 6
\pages 36--38
\mathnet{http://mi.mathnet.ru/pdma98}
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