Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method

Combinational circuit obtained from irredundant system with factorized synthesis method is considered. The conditions of a path delay fault manifestation as robust, non-robust and functional one are detected. Deriving test pairs for path delay fault is reduced to finding test patterns for $a,b$-faults of prime implicants. It allows combining test for single faults of irredundant system (that is test for multiple stuck-at faults at the gate poles of the circuit) with test for path delay faults.