Architecture selection and parameter calculation of a capacitive digital-to-analog converter for a micromechanical accelerometer

The article consider the procedure of selecting the architecture for a capacitive digital-to-analog converter (DAC) used in a successive approximation analog-to-digital converter (SAR ADC) for a micromechanical accelerometer. In comparison with the existing methods, the proposed method is based on analyzing not only the technical and technological requirements of the IC but also the technical requirements of the sensor, layout restrictions, and on calculating the parameters of the DAC. The proposed method has been used in SAR ADC design for a charge-balanced capacitive micromechanical accelerometer with measurement range of 10 g and threshold of sensitivity of 0.02 g for the bandwidth of 300 Hz. The presented method can be used in the early design stage for DAC architecture selection used in SAR ADC.