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Modelirovanie i Analiz Informatsionnykh Sistem, 2012, Volume 19, Number 2, Pages 138–144 (Mi mais225)  
This article is cited in 5 scientific papers (total in 5 papers)

On verification of PLC-programs written in the LD-language

E. V. Kuz'min, V. A. Sokolov

P. G. Demidov Yaroslavl State University
Full-text PDF (186 kB) Citations (5)
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Abstract: We discuss some questions connected with the construction of a technology of analysing correctness of Programmable Logic Controller programs. We consider an example of modeling and automated verification of PLC-programs written in the Ladder Diagram language (including timed function blocks) of the IEC 61131-3 standard. We use the Cadence SMV for symbolic model checking. Program properties are written in the linear-time temporal logic LTL.
Keywords: verification, model checking, PLC-programs, Ladder Diagrams.
Received: 05.04.2012
Document Type: Article
UDC: 519.7
Language: Russian
Citation: E. V. Kuz'min, V. A. Sokolov, “On verification of PLC-programs written in the LD-language”, Model. Anal. Inform. Sist., 19:2 (2012), 138–144
Citation in format AMSBIB
\Bibitem{KuzSok12}
\by E.~V.~Kuz'min, V.~A.~Sokolov
\paper On verification of PLC-programs written in the LD-language
\jour Model. Anal. Inform. Sist.
\yr 2012
\vol 19
\issue 2
\pages 138--144
\mathnet{http://mi.mathnet.ru/mais225}
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  • https://www.mathnet.ru/eng/mais/v19/i2/p138
    • This publication is cited in the following 5 articles:
    Citing articles in Google Scholar: Russian citations, English citations
    Related articles in Google Scholar: Russian articles, English articles
    		Моделирование и анализ информационных систем
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