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University proceedings. Volga region. Physical and mathematical sciences
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University proceedings. Volga region. Physical and mathematical sciences, 2016, Issue 2, Pages 87–102
DOI: https://doi.org/10.21685/2072-3040-2016-2-8
(Mi ivpnz247)
 

This article is cited in 4 scientific papers (total in 4 papers)

Mathematics

A method of synthesizing irredundant circuits, admitting small single fault diagnostic test sets at stuck-at faults at outputs of gates

D. S. Romanova, E. Yu. Romanovab

a Lomonosov Moscow State University, Moscow
b Russian State Social University, Moscow
Full-text PDF (544 kB) Citations (4)
References:
Abstract: Background. Testing of combinational circuits is an important theoretical problem with applications in testing and verification of VLSI. The aim of this work is to demonstrate that for an arbitrary Boolean function it is possible to construct a circuit realizing this function and allowing small single fault diagnosing test set (at stuck-at faults at outputs of gates). Materials and methods. Circuit design methods based on Zhegalkin polinomials (canonical Reed-Muller polinomial forms) were used. Results. It is established that for an arbitrary Boolean function f depending on n variables there exists an irredundant combinational circuit (in the basis {x&y,xy,1}) realizing f and admitting a single fault diagnosing test set (at stuck-at faults at outputs of gates) with constant cardinality.
Keywords: combinational circuit, fault diagnostic test set, stuck-at fault at output of gate, Shannon function, easily testable circuit.
Document Type: Article
UDC: 519.718
Language: Russian
Citation: D. S. Romanov, E. Yu. Romanova, “A method of synthesizing irredundant circuits, admitting small single fault diagnostic test sets at stuck-at faults at outputs of gates”, University proceedings. Volga region. Physical and mathematical sciences, 2016, no. 2, 87–102
Citation in format AMSBIB
\Bibitem{RomRom16}
\by D.~S.~Romanov, E.~Yu.~Romanova
\paper A method of synthesizing irredundant circuits, admitting small single fault diagnostic test sets at stuck-at faults at outputs of gates
\jour University proceedings. Volga region. Physical and mathematical sciences
\yr 2016
\issue 2
\pages 87--102
\mathnet{http://mi.mathnet.ru/ivpnz247}
\crossref{https://doi.org/10.21685/2072-3040-2016-2-8}
Linking options:
  • https://www.mathnet.ru/eng/ivpnz247
  • https://www.mathnet.ru/eng/ivpnz/y2016/i2/p87
  • This publication is cited in the following 4 articles:
    1. N. E. Aleksandrova, D. S. Romanov, “Lower Bound of the Length of a Single Fault Diagnostic Test with Respect to Insertions of a Mod-2 Adder”, Comput Math Model, 32:4 (2021), 500  crossref
    2. K. A. Popkov, “Metod postroeniya legko diagnostiruemykh skhem iz funktsionalnykh elementov otnositelno edinichnykh neispravnostei”, Preprinty IPM im. M. V. Keldysha, 2019, 081, 29 pp.  mathnet  crossref  elib
    3. K. A. Popkov, “Metod postroeniya legko diagnostiruemykh skhem iz funktsionalnykh elementov otnositelno edinichnykh neispravnostei”, PDM, 2019, no. 46, 38–57  mathnet  crossref
    4. K. A. Popkov, “Korotkie edinichnye testy dlya skhem pri proizvolnykh konstantnykh neispravnostyakh na vykhodakh elementov”, Preprinty IPM im. M. V. Keldysha, 2018, 033, 23 pp.  mathnet  crossref  elib
    Citing articles in Google Scholar: Russian citations, English citations
    Related articles in Google Scholar: Russian articles, English articles
    University proceedings. Volga region. Physical and mathematical sciences
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    References:19
     
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