Research and development of the algorithm for generating a test sequence for evaluating the power consumption of an RTL-model of processor

One of the most important trends in the development of modern microelectronics, due to a decrease in the technological process of semiconductor production and an increase in the degree of integration of microcircuits, is an increase in the performance of computer systems by increasing heterogeneity, but the energy consumption in different operating modes is a limiting factor. The article discusses the task of forming a test sequence that provides maximum switching activity for all processor units. This task belongs to the class of those problems whose complexity grows exponentially with an increasing number of input data (the number of instructions in the ISA and the dependencies between them). However, its solution can be reduced to solving the discrete optimization problem. A mathematical model is proposed for maximizing the objective function of switching activity using a genetic algorithm, for the parallel launch of which a modified architecture of the island model based on a cellular automaton is considered. The implementation of crossbreeding, mutation, and migration operators is theoretically justified. Using the algorithm, a test sequence for the developed VLIW DSP processor with RISC architecture is formed.