Investigation of register duplication method in scan compression designs

Volumes of test data are growing and test compression schemes are not enough for today’s challenges such as growth of length of logic paths and higher amount of blocking nonequivalent faults during test. These factors cause not only inflation of test sets and new requirements of storage but also increase test application time. Test point are widely used to improve testability and decrease number of blocking faults by inserting controlling and observing additional logic. Method of duplicating cells is known as a timing improving approach which is used during topology planning. In this paper it was shown that duplicating of functional register can improve testability if there are reconvergent fanouts on trigger’s output. Also it was shown that duplicating of register can reduce number of blocking faults on each combinational cell in all output paths of that register. A complexity analysis of logic path of several VLSI’s was presented. It was observed that more than 70% of all paths have one source. But there were a few paths with 7400 startpoints in one of the designs. Such paths are the most hard to test paths so duplicating of startpoint triggers of these paths would have maximum effect on testability. An algorithm of selecting registers for duplication with long output paths was proposed. Experiments on 10 industrial projects show average test time reduction 14,4% while area overhead was less than 1,2%.