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Informatsionnye Tekhnologii i Vychslitel'nye Sistemy, 2015, Issue 4, Pages 22–27 (Mi itvs205)  
COMPUTING AND SOFTWARE SYSTEMS

Embedded test and debug system with JTAG interface for CMOS digital IC

M. S. Ladnushkin

Institute for System Research, Russian Academy of Sciences
Full-text PDF (389 kB)
Abstract: Proposed test and debug system based on scan technology for CMOS digital IC. Designed debug system makes a “snapshot” of logic states of all triggers in VLSI and provides transfer of test data to tester by JTAG. Proposed debug structure is low-area (0.2% overhead) which is 0.1% lower than compared system.
Keywords: VLSI debug, JTAG, design-for-debug.
Document Type: Article
Language: Russian
Citation: M. S. Ladnushkin, “Embedded test and debug system with JTAG interface for CMOS digital IC”, Informatsionnye Tekhnologii i Vychslitel'nye Sistemy, 2015, no. 4, 22–27
Citation in format AMSBIB
\Bibitem{Lad15}
\by M.~S.~Ladnushkin
\paper Embedded test and debug system with JTAG interface for CMOS digital IC
\jour Informatsionnye Tekhnologii i Vychslitel'nye Sistemy
\yr 2015
\issue 4
\pages 22--27
\mathnet{http://mi.mathnet.ru/itvs205}
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