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This article is cited in 13 scientific papers (total in 13 papers)
A method of synthesis of irredundant circuits admitting single fault detection tests of constant length
D. S. Romanova, E. Yu. Romanovab a Lomonosov Moscow State University
b Russian State Social University, Moscow
Abstract:
A constructive proof is given that in each of the bases $B'=\{ x\mathbin{\&} y, x\oplus y, x\sim y\}$, $B_1=\{ x\mathbin{\&} y, x\oplus y, 1\}$ any $n$-place Boolean function may be implemented: a) by an irredundant combinational circuit with $n$ inputs and one output admitting (under single stuck-at faults at inputs and outputs of gates) a single fault detection test of length at most 16, b) by an irredundant combinational circuit with $n$ inputs and one output admitting (under single stuck-at faults at inputs and outputs of gates and at primary inputs) a single fault detection test of length at most $2n-2\log_2 n+O(1)$; besides, there exists an $n$-place function that cannot be implemented by an irredundant circuit admitting a detecting test whose length is smaller than $2n-2\log_2 n-\Omega(1)$, c) by an irredundant combinational circuit with $n$ inputs and three outputs admitting (under single stuck-at faults at inputs and outputs of gates and at primary inputs) a single fault detection test of length at most 17.
Keywords:
circuit of gates, fault detection test, stuck-at fault, Shannon function, easily testable circuit.
Received: 23.08.2017 Revised: 06.11.2017
Citation:
D. S. Romanov, E. Yu. Romanova, “A method of synthesis of irredundant circuits admitting single fault detection tests of constant length”, Diskr. Mat., 29:4 (2017), 87–105; Discrete Math. Appl., 29:1 (2019), 35–48
Linking options:
https://www.mathnet.ru/eng/dm1451https://doi.org/10.4213/dm1451 https://www.mathnet.ru/eng/dm/v29/i4/p87
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Abstract page: | 431 | Full-text PDF : | 57 | References: | 44 | First page: | 26 |
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