Constructing tests for networks of integrated circuits

The paper is concerned with networks whose elements are synchronous automata. A sequence of vectors in a four-(seven-) letter alphabet fed at the network input is assumed known. It is required to develop a test for a given fault by updating the terms of this sequence. A simulation procedure in this alphabet is developed. The simulation results are employed in determining the unitial segments of the sequence on which the fault can be detected and in obtaining simpler combinational equivalents which are associated with the segments. The modeling results help reduce the search of the test for a given fault.