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Avtomatika i Telemekhanika, 1985, Issue 2, Pages 139–150 (Mi at6895)  
Computers in Control

Method of binary log-antilog evaluation in hardware for fast arithmetic-logical units. I

G. G. Asatiani, O. G. Smorodinova, V. G. Chachanidze

Moscow
Full-text PDF (1834 kB)
Abstract: A method is proposed for computing the logarithmic functions through linear segment approximation with minimization of the r.m.s. error. Quantitative and probabilistic errors in computation of logarithmic functions by the method and time and hardware amount estimates of its hardware implementation are given. An algorithm of employing the method is described.

Received: 28.11.1983
Bibliographic databases:
Document Type: Article
UDC: 681.3.042, 681.325.5/6
Language: Russian
Citation: G. G. Asatiani, O. G. Smorodinova, V. G. Chachanidze, “Method of binary log-antilog evaluation in hardware for fast arithmetic-logical units. I”, Avtomat. i Telemekh., 1985, no. 2, 139–150; Autom. Remote Control, 46 (1985), 261–270
Citation in format AMSBIB
\Bibitem{AsaSmoCha85}
\by G.~G.~Asatiani, O.~G.~Smorodinova, V.~G.~Chachanidze
\paper Method of binary log-antilog evaluation in hardware for fast arithmetic-logical units.~I
\jour Avtomat. i Telemekh.
\yr 1985
\issue 2
\pages 139--150
\mathnet{http://mi.mathnet.ru/at6895}
\zmath{https://zbmath.org/?q=an:0584.65006}
\transl
\jour Autom. Remote Control
\yr 1985
\vol 46
\pages 261--270
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