Abstract:
Consideration was given to the problem of time verification of the combinational circuits, namely, to the problem of determining the false paths. The delays arising in the false paths do not manifest themselves in the circuit operational mode. At determination of the maximal circuit delay as a whole it is recommendable to detect and disregard such paths. It was proposed to reduce the problem of detecting a false path to the search of a test pattern for the stuck-at 0.1 faults of the character of the equivalent normal form corresponding to this path. Search of the test patterns comes to analyzing the conjunctions of the equivalent normal form represented compactly by the AND-OR trees and the structurally synthesized binary decision diagrams. The joint analysis of the AND-OR trees and such diagrams was oriented to reducing the computer burden at seeking the test patterns.
Citation:
A. Yu. Matrosova, S. A. Ostanin, V. Singh, “Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs”, Avtomat. i Telemekh., 2013, no. 7, 126–142; Autom. Remote Control, 74:7 (2013), 1164–1177
\Bibitem{MatOstSin13}
\by A.~Yu.~Matrosova, S.~A.~Ostanin, V.~Singh
\paper Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs
\jour Avtomat. i Telemekh.
\yr 2013
\issue 7
\pages 126--142
\mathnet{http://mi.mathnet.ru/at5462}
\transl
\jour Autom. Remote Control
\yr 2013
\vol 74
\issue 7
\pages 1164--1177
\crossref{https://doi.org/10.1134/S0005117913070084}
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Linking options:
https://www.mathnet.ru/eng/at5462
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This publication is cited in the following 8 articles:
Efanov D.V. Sapozhnikov V.V. Sapozhnikov V.V., “Using Codes With Summation of Weighted Bits to Organize Checking of Combinational Logical Devices”, Autom. Control Comp. Sci., 53:1 (2019), 1–11
A. Yu. Matrosova, V. V. Andreeva, S. V. Chernyshov, S. V. Rozhkova, D. V. Kudin, “Finding false paths in sequential circuits”, Russ. Phys. J., 60:10 (2018), 1837–1844
Anzhela Matrosova, Sergei Ostanin, Semen Chernyshov, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), 2018, 240
Dmitry Efanov, Vladimir Sapozhnikov, Valery Sapozhnikov, Dmitry Nikitin, 2015 IEEE East-West Design & Test Symposium (EWDTS), 2015, 1
Sapozhnikov V. Sapozhnikov V. Efanov D. Nikitin D., “Combinational Circuits Checking on the Base of Sum Codes With One Weighted Data BIT”, 2014 IEEE East-West Design & Test Symposium (Ewdts), IEEE, 2014
Valery Sapozhnikov, Vladimir Sapozhnikov, Dmitry Efanov, Dmitry Nikitin, Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014), 2014, 1
Valery Sapozhnikov, Vladimir Sapozhnikov, Dmitry Efanov, Anton Blyudov, Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014), 2014, 1