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Avtomatika i Telemekhanika, 2004, Issue 8, Pages 102–114 (Mi at1619)  
This article is cited in 2 scientific papers (total in 2 papers)

Technical Diagnostics

Pseudorandom test pattern generators for built-in self-testing: a power reduction method

I. A. Murashko, V. N. Yarmolik

Belarussian State University of Computer Science and Radioelectronic Engineering
Full-text PDF (262 kB) Citations (2)
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Abstract: A method of reducing the power consumption of a pseudorandom test pattern generator for scan-based built-in self-tests of digital devices is designed on the basis of formation of several test symbols in one operation cycle of the circuit.A new structure for low-power test pattern generators is described.
Presented by the member of Editorial Board: P. P. Parkhomenko

Received: 08.01.2002
English version:
Automation and Remote Control, 2004, Volume 65, Issue 8, Pages 1265–1275
DOI: https://doi.org/10.1023/B:AURC.0000038729.41847.f0
Bibliographic databases:
Document Type: Article
Language: Russian
Citation: I. A. Murashko, V. N. Yarmolik, “Pseudorandom test pattern generators for built-in self-testing: a power reduction method”, Avtomat. i Telemekh., 2004, no. 8, 102–114; Autom. Remote Control, 65:8 (2004), 1265–1275
Citation in format AMSBIB
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\paper Pseudorandom test pattern generators for built-in self-testing: a power reduction method
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\pages 102--114
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\transl
\jour Autom. Remote Control
\yr 2004
\vol 65
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\pages 1265--1275
\crossref{https://doi.org/10.1023/B:AURC.0000038729.41847.f0}
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  • https://www.mathnet.ru/eng/at/y2004/i8/p102
    • This publication is cited in the following 2 articles:
    Citing articles in Google Scholar: Russian citations, English citations
    Related articles in Google Scholar: Russian articles, English articles
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