Constructing a sequence detecting robustly testable path delay faults in sequential circuits

We propose a method for constructing a sequence of Boolean vectors of input variables that delivers test pairs $(v_1,v_2)$ of neighboring vectors in the space of input and internal variables for robustly testable path delay faults (robust Path Delay Faults (PDFs)) in sequential logic circuits. The purpose of this work is to clarify the possibility of constructing a test sequence for a given subset of paths without using scanning technologies, i.e., without additional hardware costs within the constraint of the sequence length for a single path. The experiments carried out show that test sequences can be constructed not for all paths (sometimes for none) for which test pairs exist in the combination component of the sequential circuit.